1. Technical Field of the Invention
The present invention relates to the testing of integrated circuits and, in particular, to the initiation of a stress test procedure in a low/zero power memory device during power up of the integrated circuit.
2. Description of Related Art
Reference is now made to FIG. 1 wherein there is shown a block diagram of a low/zero power memory device 10. The memory device 10 includes an nK.times.m memory array 12. As an example, the memory array may comprise a 32K.times.8 static random access memory (SRAM) array wherein n=32 and m=8. Other array configurations and memory devices (e.g., DRAM, ROM, and the like) may be provided for the array 12.
The memory device 10 further includes quartz controlled clock oscillator (with clock chain) 14. The memory array 12 and clock oscillator 14 are integrated on a single silicon chip, and are interconnected with each other at the upper eight memory locations within the memory array 12 comprising an m.times.m BiPORT(tm) array 16 in the bytes of the memory array associated with address locations 7FF8h-7FFFh. These memory locations within the memory array 12 provide user accessible clock information. This user accessible clock information comprises year, month, date, day, hour, minute and second information. It may be accessed by a user in the same manner as accessing any other stored information within the memory array 12. Timing signals for the clock oscillator 14 are supplied by a quartz crystal 18 that may be included in either the same or separate package as the memory array 12 and clock oscillator 14.
The memory device 10 is referred to as a low/zero power device because it maintains the integrity of the data stored in the memory array 12 when no (or insufficient) power is being applied to the device. To support this functionality, the memory device 10 further includes a voltage sense and switching circuit 20. The memory array 12, clock oscillator 14 and voltage sense and switching circuit 20 are integrated on a single silicon chip, and are interconnected with each other through a power supply bus 22. The voltage sense and switching circuit 20 provides power supplied from external pin power supply input 24 to the memory array 12 and clock oscillator 14 over power supply bus 22.
With a valid (i.e., at or substantially near Vcc) power supply input 24 application to the memory device 10, the memory array 12 operates in a conventional mode of operation allowing user access for read and write. Should the supply voltage provided at the power supply input 24 decay into a certain threshold range (Vpfd.sub.(MIN) to Vpfd.sub.(MAX)) that is less than Vcc but greater than the voltage necessary to maintain the integrity of the data stored in the memory array 12, the voltage sense and switching circuit 20 automatically switches the memory device 10 into a power fail deselect (pfd) mode of operation. The decayed supply voltage from power supply input 24 continues to be applied over power supply bus 22 to the memory array 12 and clock oscillator 14. However, a logic level low voltage power fail deselect signal (Vpfd) 26 is also generated by the voltage sense and switching circuit 20 and applied to the memory array 12. This voltage power fail deselect signal 26 instructs the memory array 12 to enter a write protect mode where all outputs of the memory device 10 become high impedance and all inputs are treated as "don't care." In this mode, the operational circuits 27 of the memory device 10 within the array 12, such as row decoders, column decoders, write decoders, pre-coders, post-coders, and the like, are disabled.
If the supply voltage provided at the power supply input 24 should further decay below a certain threshold (Vso) that is less than Vpfd.sub.(MIN) and approaching the minimum voltage necessary to maintain the integrity of the data stored in the memory array 12, the voltage sense and switching circuit 20 automatically switches the memory device 10 into a sleep mode of operation wherein voltage supplied from a back-up battery 28 is applied to the power supply bus 22. The back-up battery 28 provides sufficient power to the memory device 10 to maintain the integrity of the data stored in the memory array 12. The back-up battery 28 may be included in either the same or separate package as the memory array 12, clock oscillator 14 and voltage sense and switching circuit 20.
As the supply voltage provided at the power supply input 24 thereafter returns toward Vcc and rises above Vso, the voltage sense and switching circuit 20 automatically switches the memory device 10 out of the sleep mode of operation and back into the power fail deselect mode of operation. The back-up battery 28 is disconnected, and the supply voltage provided by power supply input 24 is applied to power supply bus 22. Again, while in this mode, the row decoders, column decoders, write decoders, pre-coders, post-coders and like operational circuits 27 of the memory array 12 are disabled to provide write protection to the memory array. Write protection continues to be provided until the supply voltage provided at the power supply input 24 returns to within the threshold range (Vpfd.sub.(MIN) to Vpfd.sub.(MAX)). At that point, the voltage sense and switching circuit 20 drives the Vpfd signal 26 high to automatically switch the memory device 10 out of power fail deselect mode of operation and back into the conventional mode operation.
Often, integrated circuits are tested both before and after packaging to detect latent defects. One aspect of this testing procedure is referred to as "stress testing." Stress testing of integrated circuits, such as memory devices, is typically accomplished by applying an overvoltage to the gates of the transistors in the memory array. For example, testing on a memory device rated at five volts may be performed at nine volts. To perform this test, it is common to activate multiple wordlines and columns on a simultaneous basis thus applying the testing overvoltage at each memory cell within the memory array. Defective columns and rows may then be detected. The defective portions of the device are then replaced using built-in redundancy features, or the device is discarded as defective.
With respect to low/zero power memory devices 10 like that illustrated in FIG. 1 and described above, the row decoders, column decoders, write decoders, pre-coders, post-coders and like operational circuits 27 of the memory device needed to activate multiple wordlines and columns on a simultaneous basis during stress testing are disabled until such time as the supply voltage provided at the power supply input 24 returns to within the threshold range (Vpfd.sub.(MIN) to Vpfd.sub.(MAX)). Thus, the tester must first supply Vcc above the Vpfd threshold to the device in order to perform a stress test. At this point, multiple wordlines and columns may be activated and then the device is applied with the overvoltage. The subsequent simultaneous activation and/or selection of the wordlines and columns, however, in this procedure may produce a large transient current surge within the memory device potentially inducing dynamic latch-up.
There is a need then, with respect to a low/zero power memory device, for a test mode circuit that supports entry into test mode as the external power supplied to the memory device ramps up from zero volts. With such a test mode circuit, the memory device would power up with multiple wordlines and columns activated, thus avoiding dynamic latch-up inducing transient current surges.